1. Field of the Invention
The invention relates to the design of electronic circuits and more particularly to association of constraints with design objects in electronic circuit designs.
2. Description of the Related Art
Electronic Design Automation (EDA) tools are computer software programs used to design electronic circuits. A suite of EDA tools may be used to convert a circuit design idea to a physical design including logic gates, circuit components and their interconnections. A circuit designer typically uses an EDA tool to create a schematic design of a circuit. The designer may use other FDA tools from the suite to convert the schematic to a physical layout, which specifies the shapes, positions, and dimensions of semiconductor and conductor materials such as silicon and metal. The EDA design tools can be used to in essence, translate a schematic design to a physical layout using layout rules, which specify, for example, that a particular type of transistor is to have particular dimensions and be a particular distance from other transistors in the physical layout. The physical layout can be fabricated to produce a physical implementation, which typically involves a semiconductor integrated circuit (IC) chip or printed circuit board (PCB). The integrated circuit may be, for example, an analog circuit such as an amplifier, a digital circuit such as a microprocessor, or a combination analog and digital circuit, such as a cellular telephone radio.
In one approach to circuit design, a designer creates a visual representation of a circuit design on a design canvas. A design canvas typically comprises a computer generated two-dimensional interactive user interface screen display area produced with the help of an EDA tool. The EDA tool encodes a computer system to produce the user interface that allows a designer to create such a schematic diagram by adding representations of design objects, which comprise data code structures encoded in a computer readable medium that correspond to graphical icons that represent physical circuit elements such as, transistors, resistors, digital logic gates, and other devices to the design canvas. The EDA tool user interface also may allow the designer to modify an existing schematic design by modifying existing design objects on the canvas, by adding new design objects to the canvas, and by modifying or adding connections between the design objects on the canvas. Connections between design objects in the schematic generally represent physical electrical connections between circuit elements of a circuit under development.
Design annotations can be used to communicate design intent among designers and between design tools. A design annotation may include one or more data values such as parameter values for layout rules. The data values may be, for example, text in a format that is readable by humans or by machines. A design annotation also may include one or more names associated with data values e.g., to identify specific parameters to which the data values correspond. Design annotations typically are created by a user via an EDA tool user interface or by a programming script, and are typically associated with particular design objects. Design annotations that can be recognized by a design tool or by a fabrication process are called “constraints”.
Constraint-driven design is a state-of-the-art technique for productivity enhancement in modern design automation software. A design constraint in the FDA context generally refers to a requirement imposed upon the layout of a circuit or upon the structure of circuit elements corresponding to design objects that cannot be directly captured in design parameters and that may be beyond process design rules. For example, a constraint may be imposed to help reduce second-order effects such as parasitics and to increases the likelihood that a design will meet design specifications in a smaller number of design iterations. Constraints also serve as a mechanism whereby designers can bring their own knowledge to bear to achieve design flow consistency and to achieve viable circuit structures. A constraint can be associated with one or more design objects, typically by a designer who wishes to specify information about a design object for the purpose of, for example, overriding default layout parameters provided by a base EDA tool. Moreover, for example, a constraint can specify a process parameter for use in a fabrication process in the course of fabricating an actual physical circuit based upon the design.
A design tool at one stage of an overall chip design, layout, and manufacturing process can be used to create a constraint that can be used as an input to a design tool at a different later stage of the overall design process. For instance, during an earlier design stage, a user may associate a symmetry constraint with two design objects to specify that devices corresponding to the two design objects are to be positioned with a particular orientation relative to each other. The orientation may be specified by the value of a symmetry constraint. During a layout stage, which ordinarily occurs later in the overall design process, a layout design tool may recognize the symmetry constraint and act on that constraint by laying out the devices with the specified symmetry relationship. Specifically, for example, two symmetrically constrained design objects may be laid out symmetrically (about some axis) with respect to each other within the overall circuit layout. Effectively, two objects in the design are constrained to be physically implemented as mirror images of each other. A symmetrical placement greatly increases the chances of these devices operating more identically in a practical IC manufacturing process, which tends to include variations from one device to the next. Symmetrical placement reduces the variations, and is but one example of a large number of possible constraint relationships that can be designed to achieve high yielding designs.
With the increasing complexity of custom circuit design technology, concepts like constraint-driven, connectivity-driven, and design rule-aware layout have been adopted in both in IC and PCB EDA tool domains. These capabilities generally allow multiple designers to manually encode design constraints at various stages of a design flow. Thus, designers can manually intervene in the automated design process to ensure correct connectivity and to automatically prevent design rule errors, for example. Unfortunately, today's design and manufacturing processes have significantly evolved in complexity, which when coupled with smaller device geometries, the growth in design complexity, ever increasing numbers of design rules, and a huge numbers of constraints, have contributed to a deluge of information—far too much to be entered and managed manually. Correctly creating the large number of constraints and associated them with design objects in the first place remains a significant problem.
In the past, constraints often have been manually associated with design objects representing circuit elements such as circuit instances, wires, pins, and groups of these. This earlier approach often required designers to first manually find/identify those sub-circuits which are to be constrained, to subsequently apply (again, manually) a set of constraints to those, before finally (again, manually) setting the correct values for constraint parameters. By sub-circuits, it is meant circuits that are a part of a larger circuit. All three steps can be error prone, meaning lack of accuracy, speed, and repeatability. In the past, there often was insufficient verification that the correct constraints had been added between the right devices and/or nets, that constraints had been added consistently and uniformly, and that constraint parameters had the correct values. Basically, a manual approach to the assignment of constraints often was fraught with errors. Junior designers in particular are prone to making such mistakes, which can result in non-yielding or non-fictional silicon, with significant re-mask costs incurred to correct the problem.
Recent improvements in this art include the use of a ‘constraint assistant’ software tool that can automatically identify occurrences of specific sub-circuits, which are then presented to a designer along with a suggestion of specific constraints that he or she may wish to annotate onto those sub-circuits. Unfortunately, that approach is limited. Typically, it can find only instances of a limited set of hard-coded topologies coded into the software by the vendor, and with those, can associate only a given limited set of (again hard-coded) constraints. Such hard-coded induced limitations become a problem for today's rapidly changing processes, and rapidly changing design specifications during a circuit design and implementation. Hard-coding a limited set of constraints and sub-circuits to which they may apply, is an insufficient approach to keep pace with changes and variations in design requirements after a customer has purchased and installed the EDA tool software.
Other earlier approaches have attempted to automatically analyze a circuit topology using algorithms such as signal flow (e.g., identification of the main signal flow paths in a circuit, typically from input to output such as is common for digital circuits) or by circuit equation generation. These approaches attempt to deduce circuit functionality and to automatically infer an appropriate set of constraints to enable such a circuit to be correctly manufactured with high yield. Unfortunately, such automated approaches generally do not scale well to today's complex designs and processes, and such automatically inferred set of constraints often cannot keep pace with the ever evolving process requirements.
In addition, equation based approaches often are insufficient due to attempts to model all circuit behaviors to high order polynomials (first or second order polynomials are insufficient in many cases), including non-essential behaviors, and then to attempt to appropriately constrain those. Other problems often associated with a fully automated approach to constraint assignment include errors resulting in either under or over-constrained designs, and software performance issues, as the algorithms often do not scale well to the vast number of constraints sometimes employed in today's high performance analog circuits for example, limiting the usefulness of such algorithms.
Thus, there has been a need for improvement in the creation and distribution of constraints within a circuit design whether involving an IC or a PCB. More particularly, there has been a need for improvements to both manual and automatic aspects of the creation and distribution of constraints within a design and to the coordination between these aspects. The present invention meets this need.